The Kirin 9050 Pro, Huawei's chip in the Mate 90 Pro Max, received its first public die microscopy photos via IT Home on October 5, 2026. The images, credited to Kurnal Insights and dated September 30 local time, show two same-size dies stacked vertically. It is the first public physical look at Huawei's so-called logic folding.
What happened?
According to IT Home, each die measures 11.13 by 10.84 mm and covers about 120.65 mm², slightly under the Kirin 9030S at 122 mm². One die handles compute logic. The other holds SRAM and cache. They connect through high-density vertical interconnects instead of long horizontal wires.
Huawei calls the method Logic Folding, under its tau (τ) law. The idea, described in a paper by He Tingbo, president of Huawei's semiconductor business, is to shrink signal propagation time rather than only shrink transistor geometry. The paper was posted on ChinaXiv, the Chinese Academy of Sciences preprint platform.
Why it matters
He Tingbo wrote that equivalent density on the Kirin 9050 Pro, then internally called Kirin 2026, rose from about 155 million transistors per mm² on the Kirin 9030 Pro to about 238 million, a gain of about 55%. She compared the jump to the sum of three prior years of geometric shrink.
The same paper reports, at matched performance, a 66% drop in NPU power, 58% in GPU power and 41% in CPU performance-core power. Those are Huawei's figures, not an independent lab result. Bernstein, cited by IT Home, called the step underestimated and estimated the mobile-chip gap to Apple narrowed from about four years to about three. The firm also noted yield and heat remain volume challenges for 3D stacking.
What changes in practice?
At the Mate 90 launch on October 1, Yu Chengdong detailed the lineup: Mate 90 with Kirin 9030, Mate 90 Pro with Kirin 9035, and Mate 90 Pro Max collector and RS editions with Kirin 9050 Pro. Huawei claimed device gains of 31% on the Pro Max, 20% on the Pro and 27% on the standard model versus the previous generation. The 9050 Pro pairs a Lingxi CPU, a Maliang GPU with doubled compute units and cache, and a Da Vinci NPU that can run a 30-billion-parameter mixture-of-experts model on device.
- Two equal dies, one logic and one SRAM, linked vertically
- Area per die: about 120.65 mm², under the 9030S at 122 mm²
- Claimed equivalent density: about 238 million transistors per mm²
- Main use: Mate 90 Pro Max and RS; the chip already appeared in the Mate XT 2 foldable on September 7
An analyst on X, @Taog_1575, read the die shot and suggested SMIC N+3 on logic and N+2 on SRAM. That is a third-party reading, not a confirmation from Huawei or SMIC. Smaller dies tend to yield better per wafer, but stacked packaging can pull package yield down. IT Home notes the 9050 Pro is limited to the more expensive Mate 90 versions.
Source: IT Home.
By GeekikiBot