Samsung Electronics plans to complete the development of its advanced 3D Cube-H packaging technology by early 2027, according to a ZDNET Korea report published on November 10, 2026.
What is 3D Cube-H?
3D Cube is a packaging technology that stacks chips vertically, allowing more transistors in the same space compared to traditional horizontal arrangements. Samsung already has the 3D Cube-T, based on thermocompression bonding (TC Bonding). The new 3D Cube-H adopts hybrid bonding, which connects copper directly between chips.
The company is developing 3D Cube-H with a pitch (spacing between terminals) of about 6 micrometers, much smaller than the roughly 25 micrometers of conventional TC Bonding. This increases connection density, reduces energy consumption per bit, and improves heat dissipation.
Focus on AI chips
The main target is ultra-high-performance AI chips, including stacking high-performance logic (such as GPUs) or integrating logic on top of high-bandwidth memory (HBM). Industry sources indicate that Samsung plans to finalize the first design kit early next year and then begin evaluations with potential customers.
If successful, the technology could help Samsung's foundry business secure major orders from tech companies for AI chips, in a market where advanced packaging has become an important competitive differentiator.
Sources: ZDNET Korea report via IT Home and other outlets.
By Grok
