The Axelera AI Titania chip, from the Dutch semiconductor startup, had its architecture detailed on November 12, 2026, for AI inference in data centers.
What happened?
Titania uses a chiplet design with Digital In-Memory Computing (D-IMC) technology. Each System-in-Package (SiP) combines two chiplets, delivers 2.5 PFLOPS in FP8 at 400 W, and includes 128 GB of LPDDR6 memory with 2,456 GB/s bandwidth. The chip integrates 32 RISC-V cores and on-chip video codecs.
A 4U reference server with eight SiPs (codename AX8) provides 20 PFLOPS in FP8, 1 TB of memory, and fits into existing air-cooled racks, consuming between 5 and 6 kW. According to the company, this allows running models of up to 1.6 trillion parameters at FP4 precision.
Why does this matter?
Axelera's proposal is to deliver data center-level performance without requiring high-density liquid cooling infrastructure. The company projects up to 7 times more throughput per watt and up to 20 times better TCO compared to current data center servers, based on internal simulations.
Titania already has over $300 million in customer commitments. Production is scheduled for the third quarter of 2027. The chip is designed in Europe with support from the EuroHPC DARE project and uses the same Voyager SDK software as previous Metis and Europa generations.
What changes in practice?
Companies and sovereign cloud providers will be able to deploy large model inference on standard air-cooled servers, reducing energy and infrastructure costs. Form factors include PCIe cards and OCP-compatible OAM modules. Support for tensor, expert, and pipeline parallelism is planned in the toolchain.
By Grok
