Micron detailed, in a technology webinar held on October 21, 2026, its memory and storage roadmap focused mainly on artificial intelligence workloads.
Highlights include DDR6, positioned as high-reliability memory for servers and AI data centers, with a target of more than twice the bandwidth of DDR5. LPDDR6 promises roughly 35% better power efficiency than LPDDR5. The company also discussed 1TB RDIMM capacity, after demonstrating a 512GB DDR5 RDIMM at 9,200 MT/s.
1δ node and production in 2027
These next-generation products are expected to rely on the 1δ (1-Delta) process node, successor to 1γ (1-Gamma), which is already in high-volume manufacturing. Micron expects 1δ to enter volume production in the second half of 2027, with mid-20% bit-density gains and angstrom-level process control. Manufacturing is associated with facilities in the United States (Boise).
There is no official commercial launch date for DDR6. The company currently positions it as server memory, not as a direct replacement for DDR5 in client PCs.
Vertical HBM and G11 NAND
In the HBM segment, Micron discussed vHBM (vertical HBM), in which memory is stacked directly on the compute die, and vEIM (vertical edge inference memory). The traditional HBM roadmap continues with annual generations through HBM6 in 2030.
On the storage side, G11 NAND is described with more than 400 layers, roughly 2x the bit density of G9, up to 1.5x I/O speed, and more than 25% lower energy per transfer. Production ramp is also expected in the second half of 2027.
Why it matters
The roadmap reflects demand for high-bandwidth and high-capacity memory driven by AI data centers. Micron indicated that memory supply is expected to remain tight for at least another two years. For PC gaming and consumer audiences, DDR6 still has no clear arrival timeline, and the company’s immediate focus remains on server products and HBM.
Scott DeBoer, Micron’s president and chief technology and products officer, presented the details. The company also reaffirmed its preference for 6F² architecture over 4F², citing complexity and capacitor scalability limits.
Sources
This content was produced with artificial intelligence assistance and editorially reviewed by GeekikiBot.
By GeekikiBot
